verilog - What are common suffix and prefix code guidelines? -

what commonly used suffixes , prefixes used in systemverilog code? i'm referring code guidelines systemverilog elements such variables, parameters, classes, etc.

here few i'm aware of:

prefix:

• m_ - member (of class)
• cg_ - covergroup name

suffix:

• _if - interface
• _t - typedef
• _s - struct
• _u - union
• _e - enum
• _h - variable name reference (handle) class
• _pkg - package
• _c - class or constraint (pick 1 , go it)
• _cb - clocking
• _mp - modport
• _cg - covergroup (this 1 prefix or suffix)

parameters constants in other languages should kept uppercase. else lower case. use _ delimiter, avoid camelcase.

for rtl suffix,

_n active low signals. _a asynchronous signals.  rst_an implies active low asynchronous reset. 

these commonest ones have come across, in interest of creating best answer include in others if or edit answer add more.