Configuring an RS232 to USB cable with VHDL -

i'm in process of configuring rs232 usb cable vhdl , seem have problem. don't know how configure dual-port ram. have attempted searching on answers , found code don't understand how apply code. code can found in link --> http://www.asic-world.com/examples/vhdl/ram_dp_ar_aw.html. please possible, i'm in desperate need of information.

----------------------------------------------------------------------------------  -- create date   : 14:06:22 12/08/2013  -- designer name : sarin anand k -- module name   : uart - behavioral  -- project name  : rs232 transmitter  ----------------------------------------------------------------------------------  -- spartan 3 starter kit  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all;  entity uart port(   sys_clk : in  std_logic;  --50mhz   reset   : in  std_logic;   data_in : in  std_logic_vector(7 downto 0); -- switch   load    : in  std_logic; --push button   tx      : out std_logic     );   end uart;  architecture behavioral of uart    type t_state (idle,storage,start, data, stop);  -- baud rate = 115200, bit duration required 1/115200 = 8680 ns -- 50mhz clock, period 20 ns. each bit 8680/20 = 434 clock cycles    constant bit_dur        : std_logic_vector(15 downto 0) := x"01b3";   -- 434 clocks   constant start_bit      : std_logic := '0';   constant stop_bit       : std_logic := '1';   signal   baud_cnt       : std_logic_vector(23 downto 0) := x"000000"; -- 115200   signal   baud_en        : std_logic;   signal   temp           : std_logic_vector(7 downto 0);   signal   baud_rate_cnt  : std_logic_vector(7 downto 0):=(others => '0');   signal   bit_cnt_start  : std_logic;   signal   baud_flag      : std_logic;   signal   state          : t_state;   begin ----------------------------------------------------------------------------------------------------- ---- baud clock ------------------------------------------------------------------------------------------------------  baud_rate: process(sys_clk) begin   if rising_edge(sys_clk)     if (reset = '1')        baud_cnt <= x"000000";         baud_en <= '0';      end if;       if  (baud_cnt = bit_dur)then          baud_en <= '1';                        -- data in flag          baud_cnt <= x"000000";        elsif(bit_cnt_start = '1')          baud_cnt<= baud_cnt + '1';           baud_en <= '0';      end if;   end if; end process baud_rate;  --------------------------------------------------------------------------------------------------------------- -- baud clock counter ----------------------------------------------------------------------------------------------------------------  baud_counter: process(sys_clk) begin   if(rising_edge (sys_clk))     if(reset = '1')        baud_rate_cnt <=( others => '0');        baud_flag <= '0';      end if;       if( baud_rate_cnt = "1000")          baud_flag <= '1';          baud_rate_cnt <=( others => '0');        elsif( state = data , baud_en ='1')          baud_rate_cnt <= baud_rate_cnt + '1';          baud_flag <= '0';       end if;   end if; end process baud_counter;   --------------------------------------------------------------------------------------------------------------------       -- state machine control data flow ----------------------------------------------------------------------------------------------------------------------   control_flow: process (sys_clk) begin   if(rising_edge (sys_clk))     if (reset = '1')        bit_cnt_start <= '0';        state <= idle;      end if;          case state          when  idle         =>             state           <= storage;            when storage       =>               if  (load = '1')                 state          <= start;                 bit_cnt_start  <= '1';               end if;           when start         =>                if  (baud_en ='1')               state         <= data;               end if;               when data          =>               if ((baud_en ='1') , (baud_flag = '1'))                        state          <= stop;               end if;          when stop           =>             if (baud_en = '1')              state           <= idle;                  bit_cnt_start   <= '0';            end if;          when others         =>            state             <= idle;         end case;    end if;  end process control_flow;  ------------------------------------------------------------------------------------------------------------------------   -- data transmission -------------------------------------------------------------------------------------------------------------------------  data_trans: process (sys_clk) begin   if (rising_edge(sys_clk))     if  (reset = '1')       temp <= (others => '0');      end if;       -- data mux       case state           when idle      =>             temp         <= (others => '0');            when storage   =>             temp         <= data_in;          when start     =>           tx <= start_bit;         when data      =>           tx           <= temp(0);                     if ( baud_en = '1')             temp       <=  '0' & temp(7 downto 1) ;                tx         <= temp(0);             end if;         when stop      =>           tx           <= stop_bit;         when others    =>           tx           <= '1';        end case;      end if; end process data_trans;  end behavioral;