What kind of Makefile variable assignment is this? -


i've used simple makefiles years, been assigned task of learning ins , outs of large, complicated set of autotools-generated makefiles used code base employer has bought. in these, i'm running variable declarations following:

qobject_mocsrcs = $(qobject_header:%.h=.gen/moc_%.cpp) \                   $(qobject_srcs:%.cpp=.gen/moc_%.cpp)  qobject_deps = $(qobject_mocsrcs:%.cpp=.deps/%.po)

my best guess context these set lists of names of files provided build process, eg., qobject_mocsrcs should end list of (a) .h files, (b) .cpp files, based on % stem names of set of intermediate .cpp files generated during build, in temporary directory ./gen. used store moc_%.cpp files output result of build of qt files qt's moc tool...what driving me crazy, have been unable find in make documentation i've got (mostly gnu make manual) tells me style of declaration called, can track down , grip on syntax. contents of $() sort of rules, , nearest equivalents in gnu make manual seem rules specifying target-specific variable values, have no idea whether anywhere near correct reading. can point me appropriate reference study?

this feature called substitution references, http://www.gnu.org/software/make/manual/html_node/substitution-refs.html#substitution-refs


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